Our research focus lies in the following topics:

• Energy Efficient Digitally Assisted Transmitter Architectures: The concept to replace formerly analog building blocks in the RF transceiver with fully digital ones, is based on the idea to make use of the switching performance of the transistors, which, in nm-CMOS technology, is superior to their analog performance. An important building block making use of this idea is the RF-Digital-to-Analog Converter (RF-DAC). It combines the functionality of the DAC and the mixer in a single circuit. Thus RF-DACs are a key element of digitally assisted transmitters.
  
  In our research we focus on concepts to combine the advantages of both, the classical IQ-based transmitter and the polar transmitter, while avoiding their disadvantages. This results in forms of hybrid transmitters. One line of research here is to find suitable architectures with an optimum trade-off between performance and implementation complexity. Another issue the modeling and simulation of such transmitters. While the simulation should be sufficiently close circuit simulations, the run-time needs be much faster than that of circuit simulators.

• All-digital Phase-locked Loops: A major building block in transceivers for mobile devices is the phase-locked loop (PLL). Traditionally it is used for stabilizing the local oscillator frequency at the desired value such that it can be used for signal up- and down-conversion in transmitters and receivers with low phase noise and low spurious content. A general trend is, that with evolving mobile communication standards and with the appearance of new standards, the requirements on transceivers and thus also on PLLs increase. E.g. due to the need of supporting several cellular radio access technologies, transmitters in current mobile devices for mobile devices need to have several PLLs. This is because it is currently not possible to have a single PLL (including the oscillator) to cover all cellular frequency bands of interest, as they range from around 400MHz currently up to approx. 6 GHz. Today's PLLs in transceivers for mobile devices are in a number of cases already so-called all-digital PLLs (ADPLLs) with the digitally controlled oscillator being the only remaining mixed-signal building block.
  
  We are researching methods to enlarge the frequency coverage of a ADPLLs, such that the number of oscillators required to cover all cellular frequency bands can be lowered. One such method is the use of a so-called digital-to-time converter (DTC) at the output of the ADPLL. The DTC allows to shift the phase of the ADPLL output signal in a digitally controlled way. This enables to change the frequency of the ADPLL output signal.
  In polar transmitters the ADPLL is required to generate a phase-modulated output signal with wide bandwidth. This is in contradiction to a low bandwidth of the ADPLLL to minimize phase noise. Also here the use a a DTC might prove helpful as it is located outside the ADPLL and is capable of performing the phase modulation on the ADPLL output signal.